Topics:

1. Introduction
History
2. Design Flow
First Program in Verilog
3. Verilog Syntax and Semantics
Gate Level Modeling
4. User Defined Primitives
Verilog Operators
5. Behavioral Modeling
6. Timing Control
7. Tasks and Functions
8. Test Benches
9. Memories and Finite State Machine
10. Synthesis
Assertions

A topic is covered in a two-hour meeting for a total of 20 hours.